Light emission control circuit, light source apparatus, and projection-type video display device

ABSTRACT

This light emission control circuit controls a first switching element for controlling a current that flows to a light-emitting element connected between a first node and one end of an inductor, and a second switching element for controlling a current that flows from the other end of the inductor to a second node. The light emission control circuit has a driving circuit that generates a first control signal for controlling the first switching element, and a switching control circuit that generate a second control signal for controlling the second switching element, and deactivates the second control signal in order to bring the second switching element into an off-state, during a period during which the first switching element is in an off-state.

CROSS REFERENCE

This application is a Continuation of U.S. patent application Ser. No.15/840,385 filed on Dec. 13, 2017. This application claims priority fromJapanese Patent Application No. 2016-250627 filed on Dec. 26, 2016,Japanese Patent Application No. 2017-194874 filed on Oct. 5, 2017, andJapanese Patent Application No. 2017-196626 filed on Oct. 10, 2017. Theentire disclosures of the foregoing applications are hereby incorporatedby reference in their entirely.

TECHNICAL FIELD

The invention relates to a light emission control circuit that controlslight emission in a light source apparatus in which a light-emittingelement such as a laser diode, a light emitting diode, or the like isused. The invention further relates to a light source apparatus thatuses such a light emission control circuit and a projection-type videodisplay device that uses such a light source apparatus.

RELATED ART

As techniques for adjusting brightness in a light source apparatus thatuses a light-emitting element such as a laser diode (LD), a lightemitting diode (LED), or the like, analog light control and digitallight control are known. For example, analog light control is realizedby controlling a switching regulator for driving a light-emittingelement so as to adjust the magnitude of a current that flows to thelight-emitting element. On the other hand, digital light control isrealized by controlling on/off of a switching transistor connected to alight-emitting element in series so as to adjust the length of a periodduring which a current flows to the light-emitting element.

As a related technique, Patent Literature 1 discloses a light sourcedriving apparatus that can cause the relationship between the magnitudeof a light control instruction signal and an output current to be linearover a broader light control region in order to improve the lightcontrol property of the light source in which the relationship between alight control instruction and the degree of light control is differentsignificantly between a relatively bright light control region and adark light control region.

As shown in FIG. 2 of JP-A-2015-135738, in this light source drivingapparatus, analog light control is used in which a converter circuitunit 3 that includes an inductor L1 and a switch element Q1 connected toan LED module 12 in series is controlled so as to adjust the magnitudeof an output current Io that is supplied from the converter circuit unit3 to the LED module 12.

In addition, JP-A-2009-200053 discloses a power supply apparatus thataims to improve the power efficiency in an LED lamp apparatus. As shownin FIG. 3 of JP-A-2009-200053, in this power supply apparatus, digitallight control is used in which on/off of a switching element 316connected to an LED lamp 106 in series is controlled at a predeterminedfrequency so as to adjust the length of a period during which a currentflows to the LED lamp 106.

In a case where both analog light control and digital light control areperformed in a single light source apparatus, when the circuit foranalog light control disclosed in JP-A-2015-135738 and a circuit fordigital light control disclosed in JP-A-2009-200053 are combined, thosecircuits will operate individually and independently. Therefore, evenafter a first switching element for digital light control (the switchingelement 316 of JP-A-2009-200053) transits from an on-state to anoff-state, a second switching element for analog light control (theswitch element Q1 of JP-A-2015-135738) performs an on-off operation insome cases.

During a period during which the first switching element is in anoff-state, a current does not flow to a light-emitting element, but whenthe second switching element enters an on-state, a current flows from aninductor (the inductor L1 of Patent Literature 1) to a negativeelectrode terminal of a DC power supply via the second switchingelement. Therefore, energy accumulated in the inductor is dischargedwithout being used for light emission in the light-emitting element. Asa result, there is a defect, or specifically, occurrence of wastefulpower loss in a projection-type video display device that uses such alight source apparatus.

On the other hand, it is conceivable that the second switching elementis maintained in an off-state during the period during which the firstswitching element is in an off-state, but in that case, there is a riskthat an on-period of the second switching element is shorter than anon-period that is essentially necessary. This becomes a problem in acase where an on-period of the first switching element is shorter thanthe on-period of the second switching element that is essentiallynecessary (for example, in a case where the on-duty ratio of the firstswitching element is smaller than 5%).

In such a case, sufficient energy is not accumulated in the inductor,and the energy accumulated in the inductor gradually decreases during anoff-period of the second switching element, and thus a current thatflows to the light-emitting element decreases below a current instructedin analog light control, and brightness of the light-emitting elementbecomes insufficient.

Particularly if a laser diode is used as the light-emitting element,there is a risk that the laser diode does not emit light since a currentthat flows to the laser diode does not reach the critical current oflaser oscillation. There is also a risk that the luminance of an imageprojected by a projection-type video display device that uses such alight source apparatus becomes insufficient.

SUMMARY

Accordingly, in light of the above-described issues, a first advantageof some aspects of the invention is to provide a light emission controlcircuit that can suppress discharge of energy accumulated in an inductorwithout being used for light emission and reduce power loss in a case ofperforming both analog light control and digital light control.Additionally, a second advantage of some aspects of the invention is to,when performing such light emission control, prevent reduction of acurrent that flows to a light-emitting element below a currentinstructed in analog light control even in a case where a period duringwhich a current is caused to flow to the light-emitting element indigital light control is short. Furthermore, a third advantage of someaspects of the invention is to provide a light source apparatus thatuses such a light emission control circuit, a projection-type videodisplay device that uses such a light source apparatus, and the like.

In order to solve at least a portion of the aforementioned issues, alight emission control circuit according to a first aspect of theinvention controls a first switching element for controlling a currentthat flows to a light-emitting element connected between a first nodeand one end of an inductor and a second switching element forcontrolling a current that flows from the other end of the inductor to asecond node. The light emission control circuit includes (i) a drivingcircuit that generates a first control signal for controlling the firstswitching element, and (ii) a switching control circuit that generates asecond control signal for controlling the second switching element, anddeactivates the second control signal in order to bring the secondswitching element into an off-state during at least a portion of aperiod during which the first control signal is deactivated by thedriving circuit in order to bring the first switching element into anoff-state.

According to the first aspect of the invention, in a case of performingboth analog light control and digital light control, the secondswitching element for analog light control is in an off-state during aperiod during which the first switching element for digital lightcontrol is in an off-state and a current does not flow to thelight-emitting element. That makes it possible to suppress discharge ofenergy accumulated in the inductor without being used for lightemission, and reduce power loss.

For example, in a case where a P-channel MOS transistor is used as thefirst or second switching element, the first or second control signal isactivated to a low level, and is deactivated to a high level. On theother hand, in a case where an N-channel MOS transistor is used as thefirst or second switching element, the first or second control signal isactivated to a high level, and is deactivated to a low level.

Here, the switching control circuit may maintain the second controlsignal in a deactivated state during a period during which the firstcontrol signal is deactivated if an on-duty ratio of the first controlsignal is larger than or equal to a predetermined value, and maintainthe second control signal in an activated state during a portion of theperiod during which the first control signal is deactivated if theon-duty ratio of the first control signal is smaller than thepredetermined value.

Accordingly, if the on-duty ratio of the first control signal fordigital light control is larger than or equal to the predeterminedvalue, the second switching element is maintained in an off-state bymaintaining the second control signal for analog light control in adeactivated state during the period during which the first controlsignal is deactivated. That makes it possible to suppress discharge ofenergy accumulated in the inductor without being used for lightemission, and reduce power loss, in a case of performing both analoglight control and digital light control.

In addition, if the on-duty ratio of the first control signal fordigital light control is smaller than the predetermined value, thesecond switching element is maintained in an on-state by maintaining thesecond control signal for analog light control in an activated stateduring a portion of the period during which the first control signal isdeactivated. That makes it possible to prevent reduction, below acurrent instructed in analog light control, of a current that flows tothe light-emitting element, by accumulating energy in the inductor, evenin a case where a period during which a current is caused to flow to thelight-emitting element in digital light control is short.

Here, if the on-duty ratio of the first control signal is smaller thanthe predetermined value, the switching control circuit may maintain thesecond control signal in an activated state during a predeterminedperiod after the first control signal transits from an activated stateto a deactivated state. That makes it possible to continuously increaseenergy that is accumulated in the inductor by extending a period duringwhich the second switching element is in an on-state by thepredetermined period after the first control signal is deactivated.

In addition, if the on-duty ratio of the first control signal is smallerthan the predetermined value, and the second control signal has neverbeen deactivated during a period during which the first control signalis activated, the switching control circuit may maintain the secondcontrol signal in an activated state during the predetermined period.That makes it possible to extend the pulse width of the second controlsignal only in a case where the second control signal is activated as asingle pulse during the period during which the first control signal isactivated.

Furthermore, if the on-duty ratio of the first control signal is a firstvalue, the switching control circuit may set the predetermined period toa first period, and if the on-duty ratio of the first control signal isa second value that is smaller than the first value, set thepredetermined period to a second period that is longer than the firstperiod. That makes it possible to further increase energy that isaccumulated in the inductor in a case where a period during which acurrent is caused to flow to the light-emitting element in digital lightcontrol is short.

Alternatively, the switching control circuit may adjust thepredetermined period according to a current that flows to thelight-emitting element. That makes it possible to further increaseenergy that is accumulated in the inductor in a case where the currentthat flows to the light-emitting element is smaller.

In addition, in a case where the on-duty ratio of the first controlsignal is smaller than the predetermined value, the switching controlcircuit may extend, by a first period, a period during which the secondcontrol signal is maintained in an activated state after the firstcontrol signal transits from an activated state to a deactivated stateif a current that flows to the light-emitting element when the firstcontrol signal is activated is smaller than a predetermined value, andshorten, by a second period, the period during which the second controlsignal is maintained in an activated state after the first controlsignal transits from an activated state to a deactivated state if acurrent that flows to the light-emitting element when the first controlsignal is activated is larger than the predetermined value.

In that case, it is desirable that the second period is longer than thefirst period. For example, in a case where the on-duty ratio of thefirst control signal changes from the first value to the second valuethat is larger than the first value, if the second control signal isgenerated in accordance with an extension period that was set when theon-duty ratio was the first value, a current that flows to thelight-emitting element becomes excessive. In view of this, when anextension period is set next time, the excessive current can be resolvedat an early stage by shortening the extension period by the secondperiod that is longer than the first period.

In the above description, the light emission control circuit may receiveinformation regarding the on-duty ratio of the first control signal fromoutside. That makes it possible for the switching control circuit toadjust the timing for deactivating the second control signal based onthe information regarding the on-duty ratio of the first control signal.

A light emission control circuit according to a second aspect of theinvention controls a first switching element for controlling a currentthat flows to a light-emitting element connected between a first nodeand one end of an inductor and a second switching element forcontrolling a current that flows from the other end of the inductor to asecond node, and the light emission control circuit includes a drivingcircuit that activates or deactivates a first control signal in order tobring the first switching element into an on-state or an off-state, anda switching control circuit that activates or deactivates a secondcontrol signal in order to bring the second switching element into anon-state or an off-state during a period during which the first controlsignal is activated, shortens a period during which activation of thesecond control signal is inhibited in a period during which the firstcontrol signal is deactivated, if a current that flows to thelight-emitting element when the first control signal is activated issmaller than a predetermined value, and extends the period during whichactivation of the second control signal is inhibited in the periodduring which the first control signal is deactivated, if the currentthat flows to the light-emitting element when the first control signalis activated is larger than the predetermined value.

According to the second aspect of the invention, if the current thatflows to the light-emitting element when the first control signal fordigital light control is activated is smaller than the predeterminedvalue, the period during which activation of the second control signalfor analog light control is inhibited in the period during which thefirst control signal is deactivated is shortened. Accordingly, even in acase where a period during which a current is caused to flow to thelight-emitting element in digital light control is short, it is possibleto accumulate energy in the inductor so as to prevent reduction, below acurrent instructed in analog light control, a current that flows to thelight-emitting element.

In addition, if the current that flows to the light-emitting elementwhen the first control signal for digital light control is activated islarger than the predetermined value, the period during which activationof the second control signal for analog light control is inhibited inthe period during which the first control signal is deactivated isextended. Accordingly, in a case of performing both analog light controland digital light control, it is possible to suppress discharge ofenergy accumulated in the inductor without being used for light emissionand reduce power loss.

In the light emission control circuit according to the first or secondaspect of the invention, in a case where timing for deactivating thesecond control signal is adjusted based on a current that flows to thelight-emitting element, the light emission control circuit may furtherhave a sample hold circuit that samples and holds a voltage that is inproportion to a current that flows to the light-emitting element whenthe first control signal is activated. When the on-duty ratio of thefirst control signal is small, a period during which a current flows tothe light-emitting element is shortened, but the operation speed of thesample hold circuit is higher than that of an operational amplifier, andwith the sample hold circuit, a current that flows to the light-emittingelement can be measured accurately.

A light source apparatus according to a third aspect of the inventionhas the light emission control circuit of the first or second aspect,the light-emitting element, the inductor, the first and second switchingelements, a capacitor connected between one end of the inductor and afirst node, and a diode connected between the other end of the inductorand the first node, and when the first and second switching elements arein an on-state, a current flows to the light-emitting element and theinductor, and energy is accumulated in the inductor, when the firstswitching element is in an on-state and the second switching element isin an off-state, a current flows to the light-emitting element and thediode due to energy accumulated in the inductor, and when the firstswitching element is in an off-state and the second switching element isin an on-state, a current flows to the capacitor and the inductor, andenergy is accumulated in the inductor.

According to the third aspect of the invention, it is possible toprovide a light source apparatus in which power loss is small, and thatcan accurately control brightness, by the light emission control circuitsuppressing discharge of energy accumulated in the inductor withoutbeing used for light emission, and preventing reduction in a currentthat flows to the light-emitting element even in a case where a periodduring which a current is caused to flow to the light-emitting elementin digital light control is short.

A projection-type video display device according to a fourth aspect ofthe invention has the light source apparatus according to the thirdaspect of the invention. According to the fourth aspect of theinvention, the luminance of a projected image can be controlledaccurately while reducing the power consumption of the projection-typevideo display device using the light source apparatus that canaccurately control brightness with small power loss.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention will be described with reference to the accompanyingdrawings, wherein like numbers reference like elements.

FIG. 1 is a circuit diagram of a light source apparatus that has a lightemission control circuit according to a first embodiment of theinvention.

FIG. 2 is a circuit diagram showing a configuration example of thedriving circuit and switching control circuit shown in FIG. 1.

FIG. 3 is a timing chart for illustrating an exemplary operation of thelight emission control circuit shown in FIG. 1.

FIG. 4 is a circuit diagram of a light source apparatus that has a lightemission control circuit according to a second embodiment of theinvention

FIG. 5 is a timing chart in which the light emission control circuitsshown in FIGS. 1 and 4 are compared.

FIG. 6 is a circuit diagram showing a configuration example of the clocksignal generation circuit shown in FIG. 4.

FIG. 7 is a waveform diagram showing the waveforms at the nodes of heclock signal generation circuit shown in FIG. 6.

FIG. 8 is a circuit diagram of a light source apparatus that has a lightemission control circuit according to a third embodiment of theinvention.

FIG. 9 is a circuit diagram of the switching control circuit shown inFIG. 8 and a feedback group thereof.

FIG. 10 is a timing chart for illustrating an exemplary operation in afirst light control mode.

FIG. 11 is a timing chart for illustrating an exemplary operation in asecond light control mode,

FIG. 12 is a timing chart for illustrating an exemplary operation in athird light control mode,

FIG. 13 is a timing chart for illustrating an exemplary operation in afourth light control mode.

FIG. 14 is a circuit diagram of a light source apparatus that has alight emission control circuit according to a fourth embodiment of theinvention.

FIG. 15 is a circuit diagram showing a configuration example of theswitching control circuit shown in FIG. 14.

FIG. 16 is a waveform diagram for illustrating an exemplary operation ofthe light emission control circuit shown in FIG. 14.

FIG. 17 is a circuit diagram of a light source apparatus that has alight emission control circuit according to a sixth embodiment of theinvention,

FIG. 18 is a circuit diagram showing a configuration example of theswitching control circuit shown in FIG. 17.

FIG. 19 is a waveform diagram for illustrating an exemplary operation ofthe light emission control circuit shown in FIG. 17.

FIG. 20 is a circuit diagram showing a configuration example of aswitching control circuit in a seventh embodiment.

FIG. 21 is a circuit diagram of a light source apparatus that has alight emission control circuit according to an eighth embodiment of theinvention.

FIG. 22 is a block diagram showing a configuration example of aprojection-type video display device according to one embodiment of theinvention.

DESCRIPTION OF EXEMPLARY EMBODIMENTS

Embodiments of the invention will be described below in detail withreference to the drawings. Note that the same reference numericals aregiven to the same constituent elements, and overlapping description isomitted.

First Embodiment

FIG. 1 is a circuit diagram showing a configuration example of a lightsource apparatus that has a light emission control circuit according toa first embodiment of the invention. As shown in FIG. 1, this lightsource apparatus includes a light emission control circuit 100, alight-emitting element 110, an inductor L1, a P-channel MOS transistorQP1 that is a first switching element, an N-channel MOS transistor QN1that is a second switching element, a diode D1, resistors R1 to R3, andcapacitors C1 to C4.

A power supply potential VDD on the higher potential side is supplied toa first node N1 of the light source apparatus, and a power supplypotential VSS on the lower potential side is supplied to a second nodeN2. FIG. 1 shows a case where the power supply potential VSS is a groundpotential (0 V). The transistor QP1, the light-emitting element 110, theresistor R1, the inductor L1, the transistor QN1 and the resistor R2 areconnected in series between the first node N1 and the second node N2.The light-emitting element 110 includes at least one laser diode (LD) orlight emitting diode (LED), for example, and emits light with brightnessthat is based on the magnitude of a current that is supplied.

The transistor QP1 may be connected either between the light-emittingelement 110 and the resistor R1 or between the resistor RI and theinductor L1, but in the example shown in FIG. 1, the transistor QP1 isconnected between the first node N1 and the light-emitting element 110.The transistor QP1 has a source connected to the first node N1, a drainconnected to the light-emitting element 110, and a gate to which a firstcontrol signal DDRV is applied.

The transistor QP1 is provided for digital light control, and controls acurrent that flows to the light-emitting element 110 connected betweenthe first node N1 and one end of the inductor L1. The transistor QP1 isin an on-state when the first control signal DDRV is activated to a lowlevel, and is in an off-state when the first control signal DDRV isdeactivated to a high level. When the first control signal DDRV isalternately activated and deactivated, the transistor QP1 performs aswitching operation.

The resistor R1 is connected between the light-emitting element 110 andthe one end of the inductor L1, has a small resistance value of about 50mΩ, for example, and is used for detecting a current that flows throughthe transistor QP1 and the light-emitting element 110. The transistorQN1 has a drain connected to the other end of the inductor L1, a sourceconnected to the second node N2 via the resistor R2, and a gate to whicha second control signal GATE is applied.

The transistor QN1 is provided for analog light control, and controls acurrent that flows from the other end of the inductor L1 to the secondnode N2. The transistor QN1 is in an on-state when the second controlsignal GATE is activated to a high level, and is in an off-state whenthe second control signal GATE is deactivated to a low level. When thesecond control signal GATE is alternately activated and deactivated, thetransistor QN1 performs a switching operation.

The resistor R2 is connected between the source of the transistor QN1and the second node N2, has a small resistance value of about 100 mΩ,for example, and is used for detecting a current that flows through thetransistor QN1. Note that bipolar transistors, IGBTs (Insulated GateBipolar Transistors), thyristors or the like can be used as theswitching elements, besides MOS transistors.

The diode D1 is connected between the other end of the inductor L1 andthe first node N1, and has an anode connected to the other end theinductor L1 and a cathode connected to the first node N1. For example, aSchottky barrier diode whose forward voltage is lower and whoseswitching speed is higher compared to a PN junction diode is used as thediode D1.

The capacitor C1 is connected between the first node N1 and the secondnode N2, and smooths a power supply voltage (VDD-VSS). The capacitor C4is connected between the one end of the inductor L1 and the first nodeN1, and smooths a stepped-down voltage acquired by stepping down thepower supply voltage (VDD-VSS).

Light Emission Control Circuit

The light emission control circuit 100 controls the transistors QP1 andQN1 of the light source apparatus when a digital light control signalDCS and an analog light control signal ACS are supplied from an externalmicrocomputer or the like. FIG. 1 shows an example in which the lightemission control circuit 100 is incorporated in a single semiconductordevice (IC), but the light emission control circuit 100 may beconstituted by a plurality of discrete parts or ICs. In addition, thediode D1, the resistors R1 or R2, and the like may be incorporated inthe IC.

As shown in FIG. 1, the light emission control circuit 100 includes aninternal regulator 10, level shifters 21 and 22, a driving circuit 30, aclock signal generation circuit 40, a switching control circuit 50, adriving circuit 60, and circuits including a slope compensation circuit71 to a comparator 75 provided in the feedback group of the switchingcontrol circuit 50.

The internal regulator 10 includes a reference voltage generationcircuit configured by a band gap reference circuit and the like, andgenerates an internal power supply potential VDA that is supplied to theinternal circuit of the IC, based on the power supply potential VDD. Thecapacitor C2 is connected between the output terminal of the internalregulator 10 and the second node N2, and smooths an internal powersupply voltage (VDA-VSS), The level shifters (L/S) 21 and 22 shift ahigh level potential of the digital light control signal DCS to apotential compatible with the internal circuit of the IC.

The driving circuit 30 generates the first control signal DDRV forcontrolling the transistor QP1 based on the digital light control signalDCS supplied from the level shifter 21. For example, the driving circuit30 generates an inverted signal by inverting the digital light controlsignal DCS, and generates the first control signal DDRV by causing ahigh level potential of the inverted signal to be substantially equal tothe power supply potential VDD.

In that case, when the digital light control signal DCS is activated toa high level, the transistor QP1 enters an on-state, and a current flowsto the light-emitting element 110. Therefore, by changing the duty ratioof the digital light control signal DCS, it is possible to change aperiod during which a current flows to the light-emitting element 110,so as to perform digital light control,

The clock signal generation circuit 40 includes a CR oscillation circuitand the like, and generates a clock signal CLK that has a predeterminedfrequency by performing an oscillation operation, The oscillationfrequency of the CR oscillation circuit depends on a time constant,which is the product of the capacitance value of the capacitor and theresistance value of the resistor. The resistor R3 is externally mountedon the IC in order to adjust the oscillation frequency of the CRoscillation circuit.

The switching control circuit 50 generates the second control signalGATE for controlling the transistor QN1, based on the clock signal CLK,a reset signal RST, and the digital light control signal DCS that issupplied from the level shifter 21. The second control signal GATE isapplied to the gate of the transistor QN1 via the driving circuit SOconstituted by a driver amplifier and the like. A power supply potentialsupplied to the driving circuit 60 may be the internal power supplypotential VDA, or another power supply potential that is higher than theinternal power supply potential VDA.

When the transistors QP1 and QN1 are in an on-state, a current flowsfrom the first node N1 to the second node N2 via the light-emittingelement 110, the inductor L1, and the like, and in the inductor L1,electrical energy is converted into magnetic energy, and is accumulated.When the transistor QP1 is in an on-state, and the transistor QN1 is inan off-state, the magnetic energy accumulated in the inductor L1 isdischarged as electrical energy, and a current flows to thelight-emitting element 110, the diode D1, and the like. When thetransistor QP1 is in an off-state, and the transistor QN1 is in anon-state, a current flows to the capacitor C4, the inductor L1 and thelike, and energy is accumulated in the inductor L1.

The slope compensation circuit 71 adds a bias voltage to the voltagebetween the two ends of the resistor R2 for current detection, generatesa detection signal DET, and supplies the detection signal DET to anon-inverting input terminal of the comparator 75. A current senseamplifier 72 amplifies the voltage between the two ends of the resistorR1 for current detection, generates an output signal, and supplies theoutput signal to an inverting input terminal of an operational amplifier73.

The analog light control signal ACS is supplied to a non-inverting inputterminal of the operational amplifier 73. The operational amplifier 73amplifies the difference between the voltage of the analog light controlsignal ACS and the voltage of the output signal of the current senseamplifier 72, generates an error signal ERR, and supplies the errorsignal ERR to a switch circuit (SW) 74.

The switch circuit 74 is constituted by an analog switch and the like,and is in an on-state when the digital light control signal DCS suppliedfrom the level shifter 22 is activated, and is in an off-state when thedigital light control signal DCS is deactivated. Accordingly, thevoltage of the error signal ERR generated when the transistor QP1 was inan on-state is held in the capacitor C3, and is supplied to an invertinginput terminal of the comparator 75.

The comparator 75 compares the voltage of the detection signal DETsupplied from the slope compensation circuit 71 with the voltage of theerror signal ERR, and thereby generates the reset signal RST that isbased on the comparison result, and supplies the reset signal RST to theswitching control circuit 50.

When the digital light control signal DOS is activated to a high leveland the transistor QP1 enters an on-state, the switching control circuit50 activates the second control signal GATE to a high level insynchronization with rise of the clock signal CLK. Accordingly, thetransistor QN1 enters an on-state, and a current flows from the firstnode N1 to the resistor R2 for current detection via the light-emittingelement 110, the inductor L1, and the like.

A current that flows to the inductor L1 gradually increases over time.As a current that flows to the resistor R2 via the inductor L1 and thelike increases, the voltage of the detection signal DET rises. When thevoltage of the detection signal DET exceeds the voltage of the errorsignal ERR held in the capacitor C3, the reset signal RST is activatedto a high level. Accordingly, the second control signal GATE isdeactivated to a low level, and the transistor QN1 enters an off-state.

In such a PWM (Pulse Width Modulation) operation, when the voltage ofthe analog light control signal ACS rises, the on-duty ratio of thesecond control signal GATE increases, a period during which thetransistor QN1 is in an on-state is extended, and a current that flowsto the light-emitting element 110 increases. Therefore, by changing thevoltage of the analog light control signal ACS, it is possible to changea current that flows to the light-emitting element 110 so as to performanalog light control.

On the other hand, when the transistor QP1 is in an off-state, a currentdoes not flow to the light-emitting element 110. However, when thetransistor QN1 enters an on-state, a current flows from the inductor L1to the second node N2 via the transistor QN1, and thus energyaccumulated in the inductor L1 is discharged without being used forlight emission in the light-emitting element 110. As a result, in aprojection-type video display device that uses such a light sourceapparatus, there is a defect, or specifically, occurrence of wastefulpower loss.

In view of this, in this embodiment, when alternately activating anddeactivating the second control signal GATE, the switching controlcircuit 50 deactivates the second control signal GATE in order to bringthe transistor QN1 into an off-state, during a period during which thedriving circuit 30 deactivates the first control signal DDRV in order tobring the transistor QP1 into an off-state.

FIG. 2 is a circuit diagram showing a configuration example of thedriving circuit and the switching control circuit shown in FIG. 1. Asshown in FIG. 2, the driving circuit 30 includes a level shifter 31 anda driver amplifier 32 to which the power supply potential VDD and thepower supply potential VSS (ground potential) are supplied. For example,the level shifter 31 inverts the digital light control signal DOSsupplied from the level shifter 21 shown in FIG. 1, and generates thefirst control signal DDRV. A high level potential of the first controlsignal DDRV is substantially equal to the power supply potential VDD.The first control signal DDRV is applied to the gate of the transistorQP1 (FIG. 1) via the driver amplifier 32. Note that the power supplypotential VDD and a power supply potential VHB may be supplied to thelevel shifter 31 and the driver amplifier 32.

The switching control circuit 50 includes an RS flip flop 51 and an ANDcircuit 52, for example. When the reset signal RST is at a low level,the RS flip flop 51 is set in synchronization with rise of the clocksignal CLK, and activates an output signal to a high level, and when theclock signal CLK is at a low level, the RS flip flop 51 is reset insynchronization with rise of the reset signal RST, and deactivates anoutput signal to a low level.

The AND circuit 52 generates the second control signal GATE by obtainingthe logical product of the digital light control signal DCS and anoutput signal of the RS flip flop 51. Therefore, when the digital lightcontrol signal DOS is deactivated to a low level, the first controlsignal DDRV is deactivated to a high level, and the second controlsignal GATE is deactivated to a low level.

Exemplary Operation

FIG. 3 is a timing chart for illustrating an exemplary operation of thelight emission control circuit shown in FIG. 1. In FIG. 3, theamplitudes of the signals are normalized to a fixed value. In thisexample, the driving circuit 30 inverts the digital light control signalDOS, and generates the first control signal DDRV. When the first controlsignal DDRV is activated to a low level, the transistor QP1 enters anon-state, and when the first control signal DDRV is deactivated to ahigh level, the transistor QP1 enters an off-state.

For example, in a first light control mode in which the light-emittingelement 110 emits relatively bright light, the driving circuit 30 alwaysactivates the first control signal DDRV. On the other hand, in a secondlight control mode in which the light-emitting element 110 emitsrelatively dim light (dimmer than in the first light control mode), thedriving circuit 30 adjusts the length of a period during which a currentflows to the light-emitting element 110, by alternately activating anddeactivating the first control signal DDRV in accordance with the dutyratio of the digital light control signal DCS.

In the first and second light control modes, the switching controlcircuit 50 adjusts the magnitude of a current that flows to thelight-emitting element 110, by alternately activating and deactivatingthe second control signal GATE in accordance with the voltage of theanalog light control signal ACS. Accordingly, a configuration ispossible in which, in the first light control mode in which thelight-emitting element 110 emits relatively bright light, only analoglight control is performed, and in the second light control mode inwhich the light-emitting element 110 emits relatively dim light, digitallight control is performed in addition to analog light control.

When the second control signal GATE is activated to a high level, thetransistor QN1 enters an on-state, and when the second control signalGATE is deactivated to a low level, the transistor QN1 enters anoff-state. As shown in FIG. 3, the switching control circuit 50deactivates the second control signal GATE to a low level during aperiod T0 during which the driving circuit 30 deactivates the firstcontrol signal DDRV to a high level.

With the light emission control circuit 100 according to thisembodiment, in a case of performing both analog light control anddigital light control, the transistor QN1 for analog light control ismaintained in an off-state during a period during which the transistorQP1 for digital light control is in an off-state, and a current does notflow to the light-emitting element 110. That makes it possible tosuppress discharge of energy accumulated in the inductor L1 withoutbeing used for light emission, and reduce power loss.

Second Embodiment

FIG. 4 is a circuit diagram showing a configuration example of a lightsource apparatus that has a light emission control circuit according toa second embodiment of the invention. In the second embodiment, a clocksignal generation circuit 40 a is used in place of the clock signalgeneration circuit 40 according to the first embodiment shown in FIG. 1.In the other respects, the second embodiment may be similar to the firstembodiment. In addition, FIG. 5 is a timing chart showing operations ofthe light emission control circuits shown in FIGS. 1 and 4 incomparison. In FIG. 5, the amplitudes of the signals are normalized to afixed value.

In the light emission control circuit 100 according to the firstembodiment shown in FIG. 1, the clock signal generation circuit 40operates independently from the digital light control signal DCS.Therefore, in a case where the transistor QP1 for digital light controlperforms a switching operation, and the light-emitting element 110intermittently emits light, the timing when the second control signalGATE (1) is first activated after the first control signal DDRV isactivated delays, depending on the tinning when the digital lightcontrol signal DCS is activated. Alternatively, as shown in FIG. 5, anactivation period T1 during which the second control signal GATE (1) isfirst maintained in an activated state after the first control signalDDRV is activated is shortened.

If the timing when the transistor QN1 first enters an on-state after thetransistor QP1 enters an on-state delays, in a state where sufficientenergy is not accumulated in the inductor L1, a light emission timing ofthe light-emitting element 110 delays, or a sufficient current does notflow to the light-emitting element 110. In addition, if the activationperiod T1 is short, the transistor QN1 transits to an off-state beforesufficient energy is accumulated in the inductor L1, and thus asufficient current does not flow to the light-emitting element 110. As aresult, there are cases where a light emission timing or brightness ofthe light-emitting element 110 changes, giving a sense of incongruity toan operator of the light source apparatus. Also, there is a risk thatthe luminance of a projected image changes due to a projection-typevideo display device that uses such a light source apparatus.

In view of this, in the second embodiment, a switching control circuit50 starts activation of a second control signal GATE in synchronizationwith activation of a first control signal DDRV. Accordingly, in a casewhere a light-emitting element 110 intermittently emits light accordingto digital light control, when a transistor QP1 enters an on-state, atransistor QN1 also enters an on-state, and thus it is possible toreduce change in the light emission timing or brightness of thelight-emitting element 110. In addition, it is possible to reduce changein the luminance of an image projected by a projection-type videodisplay device that has such a light source apparatus.

Furthermore, the switching control circuit 50 may set the activationperiod T1 (FIG. 5) during which the second control signal GATE is firstmaintained in an activated state after the first control signal DDRV isactivated, to be longer than or equal to a predetermined period. Here,it is desirable that the predetermined period is within a range of 95%or less of an activation period T2 during which the second controlsignal GATE is maintained in an activated state at the second time afterthe first control signal DDRV is activated.

Accordingly, in a case where the light-emitting element 110intermittently emits light according to digital light control, thetransistor QN1 transits to an off-state after the transistor QN1 entersan on-state and sufficient energy is accumulated in the inductor L1, andthus it is possible to reduce change in the brightness of thelight-emitting element 110. In this regard, in a case of masking thepulse of the second control signal GATE that is generated first afterthe first control signal DDRV is activated, generation of a short pulsecan be prevented, but there is a problem that activation of the secondcontrol signal GATE delays.

A light emission control circuit 100 shown in FIG. 4 has the clocksignal generation circuit 40 a that starts generation of a clock signalCLK in synchronization with activation of the first control signal DDRVsupplied from a level shifter 22, and the switching control circuit 50activates the second control signal GATE in synchronization with theclock signal CLK. Accordingly, the timing for activating the secondcontrol signal GATE can be synchronized with the timing for activatingthe first control signal DDRV.

FIG. 6 is a circuit diagram showing a configuration example of the clocksignal generation circuit shown in FIG. 4, and FIG. 7 is a waveformdiagram showing the waveforms of nodes of the clock signal generationcircuit shown in FIG. 6. The clock signal generation circuit 40 aoperates when an internal power supply potential VDA and a power supplypotential VSS of the IC are supplied. Hereinafter, the power supplypotential VSS is a ground potential (0 V).

As shown in FIG. 6, the clock signal generation circuit 40 a includesconstant current sources 41 and 42, a comparator 43, a buffer circuit44, an inverter 45, a P-channel MOS transistor QP2, N-channel MOStransistors QN2 to QN4, resistors R4 to R6, and a capacitor C5.

The constant current source 41 is connected between the interconnect ofthe internal power supply potential VDA of the IC and a non-invertinginput terminal of the comparator 43. The constant current source 42 isconnected between the non-inverting input terminal of the comparator 43and the interconnect of the power supply potential VSS via thetransistor QN3. For example, the constant current sources 41 and 42 arerespectively constituted by a P-channel MOS transistor and an N-channelMOS transistor that supply a constant current when a predetermined biasvoltage is applied between the gate and source thereof.

The comparator 43 compares an input potential V1 that is supplied to thenon-inverting input terminal with an input potential V2 that is suppliedto the inverting input terminal, and outputs, from the output terminal,the clock signal CLK that is based on the comparison result, The buffercircuit 44 buffers the clock signal CLK that is supplied from thecomparator 43, and outputs the clock signal CLK. The inverter 45 invertsa digital light control signal DCS, and outputs the inverted digitallight control signal DCS.

The transistor QP2 has a source connected to the non-inverting inputterminal of the comparator 43, a drain connected to the inverting inputterminal of the comparator 43, and a gate to which the digital lightcontrol signal DCS is applied. The transistor QN2 has a drain connectedto the output terminal of the comparator 43, a source connected to theinterconnect of the power supply potential VSS, and a gate to which anoutput signal of the inverter 45 is applied.

The capacitor C5 is connected between the non-inverting input terminalof the comparator 43 and the interconnect of the power supply potentialVSS. The resistor R4 is connected between the interconnect of theinternal power supply potential VDA of the IC and the inverting inputterminal of the comparator 43. The resistors R5 and R6 are connected inseries between the inverting input terminal of the comparator 43 and theinterconnect of the power supply potential VSS.

The transistor QN3 has a drain connected to the non-inverting inputterminal of the comparator 43, a source connected to the interconnect ofthe power supply potential VSS via the constant current source 42, and agate to which an output signal of the comparator 43 is applied. Thetransistor QN4 has a drain connected to the connection point between theresistors R5 and R6, a source connected to the interconnect of the powersupply potential VSS, and a gate to which an output signal of thecomparator 43 is applied.

When the digital light control signal DCS is deactivated to a low level(VSS), the transistors QP2 and QN2 are in an on-state. Accordingly, theclock signal CLK that is output from the comparator 43 is at a lowlevel, and the transistors QN3 and QN4 are in an off-state.

Therefore, the input potentials V1 and V2 that are supplied to thecomparator 43 are substantially equal to a divided voltage VH acquiredby dividing the power supply voltage VDA using the resistors R4 to R6.

VH={(R5+R6)/(R4+R5+R6)}VDA  1

In actuality, the input potentials V1 and V2 are somewhat higher thanthe divided voltage VH represented by Expression 1 due to a current thatis supplied from the constant current source 41. In addition, thecapacitor C5 is charged by the input potential V1.

When the digital light control signal DCS is activated to a high level(VDA), the transistors QP2 and QN2 enter an off-state. Accordingly, thenon-inverting input terminal and the inverting input terminal of thecomparator 43 are isolated electrically. The input potential V2 of theinverting input terminal of the comparator 43 falls to the dividedvoltage VH represented by Expression 1, which is below the inputpotential V1 of the non-inverting input terminal of the comparator 43,and thus the clock signal CLK that is output from the comparator 43transits to a high level, and the transistors QN3 and QN4 enter anon-state.

Therefore, electric charges charged in the capacitor C5 are dischargedvia the transistor QN3 and the constant current source 42, and thus theinput potential V1 of the non-inverting input terminal of the comparator43 gradually falls toward the power supply potential VSS. In addition,the input potential V2 of the inverting input terminal of the comparator43 immediately falls to a divided voltage VL represented by Expression 2below.

VL={R5/(R4+R5)}VDA  2

When the input potential V1 of the non-inverting input terminal of thecomparator 43 falls below the divided voltage VL, the clock signal CLKthat is output from the comparator 43 transits to a low level, and thetransistors QN3 and QN4 enter an off-state. Therefore, the capacitor C5is charged with a current that is supplied from the constant currentsource 41, and thus the input potential V1 of the non-inverting inputterminal of the comparator 43 gradually rises toward the internal powersupply potential VDA of the IC. In addition, the input potential V2 ofthe inverting input terminal of the comparator 43 immediately rises tothe divided voltage VH represented by Expression 1.

When the input potential V1 of the non-inverting input terminal of thecomparator 43 rises above the divided voltage VH, the clock signal CLKthat is output from the comparator 43 transits to a high level. Byrepeating such an operation, the clock signal generation circuit 40 agenerates the clock signal CLK having a predetermined frequency.

Third Embodiment

FIG. 8 is a circuit diagram showing a configuration example of a lightsource apparatus that has a light emission control circuit according toa third embodiment of the invention. In the third embodiment, aswitching control circuit 50 a is used in place of the switching controlcircuit 50 in the second embodiment shown in FIG. 4. Also, circuitsprovided in the feedback group of the switching control circuit 50 a areadded. In the other respects, the third embodiment may be similar to thesecond embodiment.

As in the second embodiment, if a transistor QN1 is maintained in anoff-state during a period during which a transistor QP1 is in anoff-state, in a case where an on-period of the transistor QP1 is short(for example, in a case where on-duty ratio is smaller than 5%), thereis a risk that an on-period of the transistor QN1 is shorter than anon-period that is essentially necessary.

In such a case, sufficient energy is not accumulated in an inductor L1,and energy accumulated in the inductor L1 gradually decreases in anoff-period of the transistor QN1, and thus a current that flows to alight-emitting element 110 decreases below a current instructed by ananalog light control signal ACS, and the luminance of the light-emittingelement 110 becomes insufficient.

In view of this, in the third embodiment, during a period during which afirst control signal DDRV is activated, the switching control circuit 50a activates or deactivates a second control signal GATE in order tobring the transistor QN1 into an on-state or an off-state, and if theon-duty ratio of the first control signal DDRV is larger than or equalto a predetermined value, maintains the second control signal GATE in adeactivated state during a period during which the first control signalDDRV is deactivated, and if the on-duty ratio of the first controlsignal DDRV is smaller than the predetermined value, maintains thesecond control signal GATE in an activated state during a portion of theperiod during which the first control signal DDRV is deactivated.

According to the third embodiment, if the on-duty ratio of the firstcontrol signal DDRV for digital light control is larger than or equal tothe predetermined value, the transistor QN1 is maintained in anoff-state by maintaining the second control signal GATE for analog lightcontrol in a deactivated state during the period during which the firstcontrol signal DDRV is deactivated. Accordingly, in a case of performingboth analog light control and digital light control, it is possible tosuppress discharge of energy accumulated in the inductor L1 withoutbeing used for light emission, and reduce power loss.

In addition, if the on-duty ratio of the first control signal DDRV fordigital light control is smaller than the predetermined value, thetransistor QN1 is maintained in an on-state by maintaining the secondcontrol signal GATE for analog light control in an activated stateduring a portion of the period during which the first control signalDDRV is deactivated. Accordingly, even in a case where a period duringwhich a current is caused to flow to the light-emitting element 110 indigital light control is short, it is possible to accumulate energy inthe inductor L1 so as to prevent reduction of a current that flows tothe light-emitting element 110 below a current instructed in analoglight control.

As shown in FIG. 8, in the feedback group of the switching controlcircuit 50 a, in addition to the circuits from the slope compensationcircuit 71 to the comparator 75 in the second embodiment that are shownin FIG. 4, a sample hold circuit 76, a current sense amplifier 77, and aselection circuit 78 are provided.

A driving circuit 30 activates or deactivates the first control signalDDRV in order to bring the transistor QP1 into an on-state or anoff-state. For example, the driving circuit 30 inverts a digital lightcontrol signal DCS supplied from a level shifter 21 so as to generate aninverted signal, and causes a high level potential of the invertedsignal to be substantially equal to a power supply potential VDD so asto generate the first control signal DDRV.

The slope compensation circuit 71 adds a bias voltage to the voltagebetween the two ends of a resistor R2 for current detection so as togenerate a detection signal DET, and supplies the detection signal DETto the non-inverting input terminal of the comparator 75. The currentsense amplifier 72 amplifies the voltage between the two ends of aresistor R1 (a current detection voltage) that is in proportion to acurrent that flows to the light-emitting element 110, so as to generatean output signal. The sample hold circuit 76 operates when the powersupply potential VDD (e.g., 50 V) and a power supply potential VHB(e.g., 45 V) are supplied thereto, and samples and holds a currentdetection voltage that is in proportion to a current that flows to thelight-emitting element 110 when the first control signal DDRV isactivated.

When the on-duty ratio of the first control signal DDRV decreases, aperiod during which a current flows to the light-emitting element 110 isshortened, but the operation speed of the sample hold circuit 76 ishigher than that of the operational amplifier, and the sample holdcircuit 76 can accurately measure a current that flows to thelight-emitting element 110. The current sense amplifier 77 amplifies thecurrent detection voltage held in the sample hold circuit 76 so as togenerate an output signal.

The selection circuit 78 selects either an output signal of the currentsense amplifier 72 or an output signal of the current sense amplifier 77in accordance with a selection signal supplied from the switchingcontrol circuit 50 a, and supplies the selected signal to the invertinginput terminal of the operational amplifier 73. The analog light controlsignal ACS is supplied to the non-inverting input terminal of theoperational amplifier 73. The operational amplifier 73 amplifies thedifference between the voltage of the analog light control signal ACSand the voltage of the signal selected by the selection circuit 78, soas to generate an error signal ERR, and supplies the error signal ERR tothe switch circuit 74.

The switch circuit 74 enters an off-state in accordance with a controlsignal supplied from the switching control circuit 50 a, during a periodduring which the digital light control signal DCS is deactivated to alow level and a predetermined mask period, and is in an on-state duringa period other than those periods. Accordingly, the voltage of the errorsignal ERR generated when the switch circuit 74 was in an on-state isheld in a capacitor C3, and is supplied to the inverting input terminalof the comparator 75.

The comparator 75 compares the voltage of the detection signal DETsupplied from the slope compensation circuit 71 with the voltage of theerror signal ERR so as to generate a comparison result signal COMP thatis based on the comparison result, and supplies the comparison resultsignal COMP to the switching control circuit 50 a.

The switching control circuit 50 a activates or deactivates the secondcontrol signal GATE based on the clock signal CLK, the comparison resultsignal COMP, and the digital light control signal DCS supplied from thelevel shifter 21 in order to bring the transistor QN1 into an on-stateor an off-state.

FIG. 9 is a circuit diagram showing a configuration example of theswitching control circuit shown in FIG. 8 and the circuits of thefeedback group thereof. In this example, the switching control circuit50 a includes a RS flip flop 51, an AND circuit 52, an inverter 53, adelay circuit 54, switch circuits 55 and 56, an OR circuit 57, and acondition setting circuit 58.

When an output signal of the OR circuit 57 is at a low level, the RSflip flop 51 is set in synchronization with rise of the clock signalCLK, and activates the second control signal GATE to a high level, andwhen the clock signal CLK is at a low level, the RS flip flop 51 isreset in synchronization with rise of an output signal of the OR circuit57, and deactivates the second control signal GATE to a low level.

The inverter 53 inverts the digital light control signal DCS that issupplied from the level shifter 21 (FIG. 8) so as to generate an outputsignal. For example, the delay circuit 54 is constituted by a pluralityof delay elements such as inverters that cause a gate delay, or aresistor, a capacitor and the like, and delays the output signal of theinverter 53 by a delay time TD.

The AND circuit 52 generates an output signal by obtaining the logicalproduct of an output signal of the inverter 53 and an output signal ofthe delay circuit 54. The output signal of the AND circuit 52 is set toa low level at the time when the digital light control signal DCS isactivated, and is set to a high level at the time when the delay time TDhas elapsed since the digital light control signal DCS was deactivated.

The switch circuits 55 and 56 are constituted by an analog switch andthe like, and select either an output signal of the inverter 53 or anoutput signal of the AND circuit 52. The OR circuit 57 generates anoutput signal by obtaining the logical sum of the signal selected by theswitch circuits 55 and 56 and the comparison result signal COMP that isoutput from the comparator 75. The output signal of the OR circuit 57 issupplied to the reset terminal of the RS flip flop 51.

When the signal selected by the switch circuits 55 and 56 is set to ahigh level, or when the voltage of the detection signal DET rises abovethe voltage of the error signal ERR and the comparison result signalCOMP is set to a high level, the OR circuit 57 generates a high-leveloutput signal. Accordingly, the RS flip flop 51 is reset, and the secondcontrol signal GATE is deactivated.

The condition setting circuit 58 is configured by a logic circuitincluding a combinational circuit or a sequential circuit, and the like,and controls the switch circuits 55 and 56, the switch circuit 74, andthe selection circuit 78. For example, the selection circuit 78 includesswitch circuits 78 a and 78 b constituted by an N-channel MOS transistoror various types of transistors and the like, selects either an outputsignal of the current sense amplifier 72 or an output signal of thecurrent sense amplifier 77, and supplies the selected signal to theinverting input terminal of the operational amplifier 73.

First Exemplary Operation

In a first exemplary operation, a light emission control circuit 100(FIG. 8) receives, from an external microcomputer or the like,information regarding the on-duty ratio of the digital light controlsignal DCS, namely, information regarding the on-duty ratio of the firstcontrol signal DDRV. Accordingly, the switching control circuit 50 a canadjust the timing for deactivating the second control signal GATE, basedon the information regarding the on-duty ratio of the first controlsignal DDRV.

For example, four types of light control modes are set according to theon-duty ratio of the first control signal DDRV, and information forspecifying the current light control mode is supplied to the conditionsetting circuit 58. The condition setting circuit 58 sets a conditionfor deactivating the second control signal GATE based on the informationfor specifying the current light control mode, and generates selectionsignals SEL1 to SEL4.

In a first light control mode, the on-duty ratio of the first controlsignal DDRV is 100%, and only analog light control is performed. In asecond light control mode, the on-duty ratio of the first control signalDDRV is larger than or equal to 50% and smaller than 100%, in a thirdlight control mode, the on-duty ratio of the first control signal DDRVis larger than or equal to 5% and smaller than 50%, and in a fourthlight control mode, the on-duty ratio of the first control signal DDRVis larger than 0% and smaller than 5%. In the second to fourth lightcontrol modes, both analog light control and digital light control areperformed. Note that in this embodiment or the other embodiments, theremay be a lower limit value (e.g., 1%) to the on-duty ratio.

In the first and second light control modes, the condition settingcircuit 58 activates the selection signal SEL1, and deactivates theselection signal SEL2. Accordingly, the switch circuit 78 a enters anon-state, and the switch circuit 78 b enters an off-state, and thus anoutput signal of the current sense amplifier 72 is supplied to theinverting input terminal of the operational amplifier 73.

On the other hand, in the third and fourth light control modes, thecondition setting circuit 58 deactivates the selection signal SEL1, andactivates the selection signal SEL2. Accordingly, the switch circuit 78a enters an off-state, and the switch circuit 78 b enters an on-state,and thus an output signal of the current sense amplifier 77 is suppliedto the inverting input terminal of the operational amplifier 73.

Therefore, if the on-duty ratio of the first control signal DDRV islarger than or equal to 50%, the output signal of the current senseamplifier 72 for amplifying a current detection voltage that is inproportion to a current that flows to the light-emitting element 110 isused for adjusting the timing for deactivating the second control signalGATE. On the other hand, if the on-duty ratio of the first controlsignal DDRV is smaller than 50%, the output signal of the current senseamplifier 77 for amplifying a current detection voltage held in thesample hold circuit 76 is used for adjusting the timing for deactivatingthe second control signal GATE.

In addition, in the first to third light control modes, the conditionsetting circuit 58 activates the selection signal SEL3, and deactivatesthe selection signal SEL4. Accordingly, the switch circuit 55 enters anon-state, and the switch circuit 56 enters an off-state, and thus anoutput signal of the inverter 53 is supplied to one input terminal ofthe OR circuit 57. The comparison result signal COMP that is output fromthe comparator 75 is supplied to the other input terminal of the ORcircuit 57.

When the digital light control signal DCS is deactivated to a low level,or when the voltage of the detection signal DET rises above the voltageof the error signal ERR and the comparison result signal COMP is set toa high level, the OR circuit 57 generates a high-level output signal.Accordingly, the RS flip flop 51 is reset, and the second control signalGATE is deactivated. Therefore, if the on-duty ratio of the firstcontrol signal DDRV is larger than or equal to 5%, the second controlsignal GATE is maintained in a deactivated state during a period duringwhich the first control signal DDRV is deactivated.

On the other hand, in the fourth light control mode, the conditionsetting circuit 58 deactivates the selection signal SEL3, and activatesthe selection signal SEL4. Accordingly, the switch circuit 55 enters anoff-state, and the switch circuit 56 enters an on-state, and thus anoutput signal of the AND circuit 52 is supplied to one input terminal ofthe OR circuit 57. The comparison result signal COMP that is output fromthe comparator 75 is supplied to the other input terminal of the ORcircuit 57.

When the delay time TD has elapsed after the digital light controlsignal DCS is deactivated to a low level, or when the voltage of thedetection signal DET rises above the voltage of the error signal ERR andthe comparison result signal COMP is set to a high level, the OR circuit57 generates a high-level output signal. The RS flip flop 51 is therebyreset, and the second control signal GATE is deactivated. Therefore, ifthe on-duty ratio of the first control signal DDRV is smaller than 5%,the second control signal GATE is maintained in an activated stateduring a portion of a period during which the first control signal DDRVis deactivated.

Note that a current that flows to the inductor L1 (FIG. 8) graduallyincreases after the transistor QN1 enters an on-state, and thus if theon-duty ratio of the first control signal DDRV is small, the comparisonresult signal COMP that is output from the comparator 75 is kept at alow level before and after the timing when the first control signal DDRVis deactivated.

FIGS. 10 to 13 are timing charts for illustrating exemplary operationsin the first to fourth light control modes, respectively. As shown inFIG. 10, in the first light control mode, the digital light controlsignal DCS is always activated to a high level, and analog light controlis performed by the second control signal GATE being activated to a highlevel and deactivated to a low level. On the other hand, as shown inFIGS. 11 to 13, in the second to fourth light control modes, the digitallight control signal DCS is also activated to a high level anddeactivated to a low level, and both analog light control and digitallight control are performed.

As shown in FIGS. 11 and 12, in the second and third light controlmodes, the second control signal GATE is activated to a high level insynchronization with rise of the digital light control signal DCS. Also,the second control signal GATE is forcefully deactivated to a low levelin synchronization with fall of the digital light control signal DCS.

As shown in FIG. 13, in the fourth light control mode, the secondcontrol signal GATE is activated to a high level in synchronization withrise of the digital light control signal DCS. On the other hand, interms of the deactivation of the second control signal GATE, the secondcontrol signal GATE is not synchronized with fall of the digital lightcontrol signal DCS, and is maintained in an activated state during thedelay time TD (a predetermined period) after fall of the digital lightcontrol signal DCS, and then deactivated to a low level.

Note that as shown in FIG. 11, in the second light control mode, thecondition setting circuit 58 may generate a mask signal MASK that isactivated during a predetermined mask period (MASK TIME) immediatelyafter the digital light control signal DCS transitioned to an activatedstate. The mask signal MASK is used for turning off the switch circuit74. Accordingly, it is possible to avoid the influence of a measurementerror caused by the operation speed of the current sense amplifier 72being low.

In addition, as shown in FIGS. 12 and 13, in the third and fourth lightcontrol modes, the condition setting circuit 58 may generate a samplehold signal SHS that is activated during a predetermined sample holdperiod (S/H TIME) immediately before the digital light control signalDCS transits to a deactivated state.

The sample hold signal SHS is used for causing the sample hold circuit76 to perform a sample hold operation. Accordingly, the sample holdcircuit 76 can perform the sample hold operation after a current thatflows to the light-emitting element 110 is stabilized. Alternatively,the sample hold signal SHS may be supplied from an externalmicrocomputer or the like to the light emission control circuit 100(FIG. 8).

In this manner, if the on-duty ratio of the first control signal DDRV issmaller than a predetermined value (in this example, 5%), the switchingcontrol circuit 50 a maintains the second control signal GATE in anactivated state during a predetermined period after the first controlsignal DDRV transits from an activated state to a deactivated state.That makes it possible to extend a period during which the transistorQN1 is in an on-state by the predetermined period after the firstcontrol signal DDRV is deactivated, and continuously increase energythat is accumulated in the inductor L1.

At this time, if the on-duty ratio of the first control signal DDRV issmaller than the predetermined value, and the second control signal GATEhas never been deactivated during a period during which the firstcontrol signal DDRV is activated, the switching control circuit 50 a maymaintain the second control signal GATE in an activated state during thepredetermined period. Accordingly, only in a case where the secondcontrol signal GATE is activated as a single pulse during the periodduring which the first control signal DDRV is activated, the pulse widthof the second control signal GATE can be extended.

Therefore, for example, in a case where the comparison result signalCOMP has ever been at a high level during a period during which thedigital light control signal DCS is activated, the condition settingcircuit 58 activates the selection signal SEL3, and deactivates theselection signal SEL4. That state is cancelled when the digital lightcontrol signal DCS is activated next time.

Second Exemplary Operation

In a second exemplary operation, even if information regarding theon-duty ratio of the digital light control signal DCS is not suppliedfrom outside, the condition setting circuit 58 can set a condition fordeactivating the second control signal GATE. For example, the conditionsetting circuit 58 generates the selection signals SEL1 to SEL4 based onthe digital light control signal DCS and the comparison result signalCOMP that is output from the comparator 75.

In a case where the comparison result signal COMP has ever been at ahigh level during a period during which the digital light control signalDCS is activated, the condition setting circuit 58 determines that theon-duty ratio of the first control signal DDRV is larger than or equalto a predetermined value, and activates the selection signals SEL1 andSEL3, and deactivates the selection signals SEL2 and SEL4.

Accordingly, the switch circuit 78 a enters an on-state, and the switchcircuit 78 b enters an off-state, and thus an output signal of thecurrent sense amplifier 72 is supplied to the inverting input terminalof the operational amplifier 73. In addition, the switch circuit 55enters an on-state, and the switch circuit 56 enters an off-state, andthus an output signal of the inverter 53 is supplied to one inputterminal of the OR circuit 57. The comparison result signal COMP that isoutput from the comparator 75 is supplied to the other input terminal ofthe OR circuit 57,

When the digital light control signal DOS is deactivated to a low level,or when the voltage of the detection signal DET rises above the voltageof the error signal ERR and the comparison result signal COMP is set toa high level, the OR circuit 57 generates a high-level output signal.Accordingly, the RS flip flop 51 is reset, and the second control signalGATE is deactivated. Therefore, if the on-duty ratio of the firstcontrol signal DDRV is larger than or equal to the predetermined value,the second control signal GATE is maintained in a deactivated stateduring a period during which the first control signal DDRV isdeactivated.

On the other hand, in a case where the comparison result signal COMP hasnever been activated during a period during which the digital lightcontrol signal DCS is activated, the condition setting circuit 58determines that the on-duty ratio of the first control signal DDRV issmaller than the predetermined value, deactivates the selection signalsSEL1 and SEL3, and activates the selection signals SEL2 and SEL4.

Accordingly, the switch circuit 78 a enters an off-state, and the switchcircuit 78 b enters an on-state, and thus an output signal of thecurrent sense amplifier 77 is supplied to the inverting input terminalof the operational amplifier 73. In addition, the switch circuit 55enters an off-state, and the switch circuit 56 enters an on-state, andan output signal of the AND circuit 52 is supplied to one input terminalof the OR circuit 57. The comparison result signal COMP that is outputfrom the comparator 75 is supplied to the other input terminal of the ORcircuit 57.

When the delay time TD has elapsed after the digital light controlsignal DCS was deactivated to a low level, or when the voltage of thedetection signal DET rises above the voltage of the error signal ERR andthe comparison result signal COMP is set to a high level, the OR circuit57 generate a high-level output signal. Accordingly, the RS flip flop 51is reset, and the second control signal GATE is deactivated. Therefore,if the on-duty ratio of the first control signal DDRV is smaller thanthe predetermined value, the second control signal GATE is maintained inan activated state during a portion of a period during which the firstcontrol signal DDRV is deactivated.

Note that a current that flows to the inductor L1 (FIG. 8) graduallyincreases after the transistor QN1 enters an on-state, and thus if theon-duty ratio of the first control signal DDRV is small, the comparisonresult signal COMP that is output from the comparator 75 is kept at alow level before and after the timing when the first control signal DDRVis deactivated.

Fourth Embodiment

FIG. 14 is a circuit diagram showing a configuration example of a lightsource apparatus that has a light emission control circuit according toa fourth embodiment of the invention. In the fourth embodiment, aswitching control circuit 50 b is used in place of the switching controlcircuit 50 in the second embodiment shown in FIG. 4. Also, a comparator79, an inverter 80, an up-down counter 81, and a pulse width extensioncircuit 82 are added. In the other respects, the fourth embodiment maybe similar to the second embodiment.

A slope compensation circuit 71 adds a bias voltage to the voltagebetween the two ends of a resistor R2 for current detection so as togenerate a detection signal DET, and supplies the detection signal DETto a non-inverting input terminal of a comparator 75. A current senseamplifier 72 amplifies the voltage between the two ends of a resistor R1that is in proportion to a current that flows to a light-emittingelement 110 (a current detection voltage), so as to generate an outputsignal. The comparator 75 compares the voltage of the detection signalDET that is supplied from the slope compensation circuit 71 with thevoltage of an error signal ERR, so as to generate a comparison resultsignal COMP that is based on the comparison result, and supplies thecomparison result signal COMP to the switching control circuit 50 b.

The comparator 79 compares the voltage of an output signal of thecurrent sense amplifier 72 with the voltage of an analog light controlsignal ACS so as to generate an output signal ICOMP that is based on thecomparison result. The output signal ICOMP of the comparator 79 is setto a high level if a current that flows to the light-emitting element110 is smaller than a predetermined value, and is set to a low level ifa current that flows to the light-emitting element 110 is larger thanthe predetermined value. Note that a certain amount of response time isrequired for the output voltage of the current sense amplifier 72 andthe output level of the comparator 79 to change, and thus the previousstate is maintained at a time point when a digital light control signalDCS falls. The output signal ICOMP of the comparator 79 is supplied tothe up-down counter 81.

The inverter 80 inverts the digital light control signal DCS that issupplied from a level shifter 22, and supplies the inverted digitallight control signal DCS to the up-down counter 81. The up-down counter81 performs a count-up operation or a count-down operation insynchronization with fall of the digital light control signal DCS inaccordance with the output signal ICOMP of the comparator 79.

For example, when the power supply is on, the count value of the up-downcounter 81 is reset to the initial value. The up-down counter 81increments the count value in synchronization with fall of the digitallight control signal DCS when the output signal ICOMP of the comparator79 is at a high level, and decrements the count value when the outputsignal COMP of the comparator 79 is at a low level.

For example, the pulse width extension circuit 82 is constituted by alogic circuit that includes a combinational circuit or a sequentialcircuit, generates a selection signal SEL used for selecting anactivation period (a pulse width) of a second control signal GATE basedon the count value of the up-down counter 81, and outputs the selectionsignal SEL to the switching control circuit 50 b.

The switching control circuit 50 b activates or deactivates the secondcontrol signal GATE based on a clock signal CLK, the comparison resultsignal COMP, the selection signal SEL, and the digital light controlsignal DCS that is supplied from a level shifter 21, in order to bring atransistor QN1 into an on-state or an off-state.

FIG. 15 is a circuit diagram showing a configuration example of theswitching control circuit shown in FIG. 14. In this example, theswitching control circuit 50 b includes an RS flip flop 51, an ANDcircuit 52, an inverter 53, an OR circuit 57, and a variable delaycircuit 59.

When an output signal of the OR circuit 57 is at a low level, the RSflip flop 51 is set in synchronization with rise of the clock signalCLK, and activates the second control signal GATE to a high level, andwhen the clock signal CLK is at a low level, the RS flip flop 51 isreset in synchronization with rise of an output signal of the OR circuit57, and deactivates the second control signal GATE to a low level.

The inverter 53 inverts the digital light control signal DCS so as togenerate an output signal, and supplies the output signal to thevariable delay circuit 59. The variable delay circuit 59 includes aplurality of delay circuits to which output signals of the inverter 53are supplied in parallel, and a selection circuit 59 a for selecting onesignal from an output signal of the inverter 53 and output signals ofthe delay circuits. For example, each of the delay circuits isconstituted by a plurality of delay elements such as inverters thatcause a gate delay, or a resistor, a capacitor, and the like, and theselection circuit 59 a is constituted by a plurality of analog switchesand the like.

The delay circuits have delay times TD1, TD2, . . . , TDn that aredifferent from each other, and delay the digital light control signalDCS inverted by the inverter 53. In addition, the selection circuit 59 aselects the delay time TD of the digital light control signal DCSinverted by the inverter 53, in accordance with the selection signal SELsupplied from the pulse width extension circuit 82 (FIG. 14).

The AND circuit 52 generate an output signal by obtaining the logicalproduct of an output signal of the inverter 53 and an output signal ofthe variable delay circuit 59. The output signal of the AND circuit 52is set to a low level at the time when the digital light control signalDCS is activated, and is set to a high level at the time when the delaytime TD has elapsed after the digital light control signal DCS wasdeactivated (TD≥0).

The OR circuit 57 generates an output signal by obtaining the logicalsum of an output signal of the AND circuit 52 and the comparison resultsignal COMP that is output from the comparator 75 (FIG. 14). The outputsignal of the OR circuit 57 is supplied to a reset terminal of the RSflip flop 51. When an output signal of the AND circuit 52 is set to ahigh level, or when the voltage of the detection signal DET rises abovethe voltage of the error signal ERR and the comparison result signalCOMP is set to a high level, the OR circuit 57 generates a high-leveloutput signal. Accordingly, the RS flip flop 51 is reset, anddeactivates the second control signal GATE.

Exemplary Operation

An exemplary operation of the light emission control circuit accordingto the fourth embodiment of the invention will be described withreference to FIGS. 14 to 16. FIG. 16 is a waveform diagram forillustrating an exemplary operation of the light emission controlcircuit shown in FIG. 14.

When the digital light control signal DCS is activated to a high level,a first control signal DDRV is activated to a low level, a transistorQP1 enters an on-state, and a current ILD flows to the light-emittingelement 110. The switching control circuit 50 b activates or deactivatesthe second control signal GATE in order to bring the transistor QN1 intoan on-state or an off-state, during a period during which the firstcontrol signal DDRV is activated.

When the second control signal GATE is activated to a high level insynchronization with activation of the digital light control signal DCS,the transistor QN1 enters an on-state, and a current IL flows to theinductor Li, The current IL that flows to the inductor L1 graduallyincreases over time. During the period shown in FIG. 16, the current ILthat flows to the inductor L1 is small, and thus the comparison resultsignal COMP that is output from the comparator 75 is at a low level,

As shown in FIG. 16, if the current ILD that flows to the light-emittingelement 110 when the first control signal DDRV is activated is smallerthan a predetermined value, the output signal ICOMP of the comparator 79is set to a high level, and the up-down counter 81 is set to an count-upmode.

After that, when the digital light control signal DCS is deactivated toa low level, the first control signal DDRV is deactivated to a highlevel, the transistor QP1 enters an off-state, and the current ILD tothe light-emitting element 110 stops. In addition, the up-down counter81 increments the count value in synchronization with fall of thedigital light control signal DCS, and thus the count value of theup-down counter 81 increases above the previous value.

The pulse width extension circuit 82 outputs, to the switching controlcircuit 50 b, the selection signal SEL for selecting an output signal ofthe delay circuit having the delay time TD that is based on thedifference between the count value and the initial value. In theswitching control circuit 50 b, the selection circuit 59 a selects theoutput signal of the delay circuit having the delay time TD that hasincreased. Accordingly, after the delay time TD has elapsed since thedigital light control signal DCS was deactivated, an output signal ofthe AND circuit 52 is set to a high level, and an output signal of theOR circuit 57 is set to a high level, and the RS flip flop 51deactivates the second control signal GATE.

Here, a period during which an output signal of the AND circuit 52 is ata high level corresponds to a period during which activation of thesecond control signal GATE for analog light control is inhibited.Therefore, when the delay time TD increases, the period during whichactivation of the second control signal GATE for analog light control isinhibited in a period during which the first control signal DDRV fordigital light control is deactivated is shortened.

When the second control signal GATE is deactivated to a low level, thetransistor QN1 enters an off-state, and the current IL that flows to theinductor L1 decreases. By repeating such an operation every time thedigital light control signal DCS is activated and deactivated, the pulsewidth of the second control signal GATE increases gradually.

Next, if the current ILD that flows to the light-emitting element 110when the digital light control signal DCS is activated to a high levelexceeds the predetermined value, the output signal ICOMP of thecomparator 79 is set to a low level, and the up-down counter 81 is setto a count-down mode.

When the digital light control signal DOS is deactivated to a low level,the first control signal DDRV is deactivated to a high level, thetransistor QP1 enters an off-state, and the current ILD to thelight-emitting element 110 stops. Also, the up-down counter 81decrements the count value in synchronization with fall of the digitallight control signal DCS, and thus the count value decreases below theprevious value.

The pulse width extension circuit 82 outputs, to the switching controlcircuit 50 b, the selection signal SEL for selecting an output signal ofthe delay circuit having the delay time TD that is based on thedifference between the count value and the initial value. In theswitching control circuit 50 b, the selection circuit 59 a selects theoutput signal of the delay circuit having the delay time TD that hasdecreased. Accordingly, after the delay time TD has elapsed since thedigital light control signal DOS was deactivated, the second controlsignal GATE is deactivated to a low level.

In a case where the count value of the up-down counter 81 became smallerthan or equal to a lower limit value, the pulse width extension circuit82 outputs the selection signal SEL for selecting an output signal ofthe inverter 53 to the switching control circuit 50 b. In the switchingcontrol circuit 50 b, the selection circuit 59 a selects the outputsignal of the inverter 53. Accordingly, when the digital light controlsignal DCS is deactivated, the second control signal GATE is deactivatedto a low level.

Here, a period during which an output signal of the AND circuit 52 is ata high level corresponds to a period during which activation of thesecond control signal GATE for analog light control is inhibited.Therefore, when the delay time TD decreases, the period during whichactivation of the second control signal GATE for analog light control isinhibited in a period during which the first control signal DDRV fordigital light control is deactivated is extended. This period isextended to be equal to the deactivation period of the first controlsignal DDRV at most.

When the second control signal GATE is deactivated to a low level, thetransistor QN1 enters an off-state, and the current IL that flows to theinductor L1 decreases. By repeating increase and decrease in the pulsewidth of the second control signal GATE every time the digital lightcontrol signal DCS is activated and deactivated, the pulse width of thesecond control signal GATE is settled at an appropriate value.

In this manner, according to the fourth embodiment, if a current thatflows to the light-emitting element 110 when the first control signalDDRV for digital light control is activated is smaller than thepredetermined value, the period during which activation of the secondcontrol signal GATE for analog light control is inhibited in a periodduring which the first control signal DDRV is deactivated is shortened.Accordingly, even in a case where a period during which a current iscaused to flow to the light-emitting element 110 in digital lightcontrol is short, it is possible to accumulate energy in the inductor L1so as to prevent reduction of a current that flows to the light-emittingelement 110 below a current instructed in analog light control.

In addition, if a current that flows to the light-emitting element 110when the first control signal DDRV for digital light control isactivated is larger than the predetermined value, the period duringwhich activation of the second control signal GATE for analog lightcontrol is inhibited in the period during which the first control signalDDRV is deactivated is extended. Accordingly, in a case of performingboth analog light control and digital light control, it is possible tosuppress discharge of energy accumulated in the inductor L1 withoutbeing used for light emission, and reduce power loss.

Modified Example of Fourth Embodiment

Similarly to the light emission control circuit 100 shown in FIG. 8, thelight emission control circuit 100 shown in FIG. 14 may include a samplehold circuit 76 that samples and holds a current detection voltage thatis in proportion to a current that flows to the light-emitting element110 when the first control signal DDRV is activated, and the currentsense amplifier 77 that amplifies the current detection voltage held inthe sample hold circuit 76, and generates an output signal. In thatcase, the output signal of the current sense amplifier 77 is supplied tothe inverting input terminal of the comparator 79.

Fifth Embodiment

In a fifth embodiment of the invention, the switching control circuit 50a in the third embodiment shown in FIG. 9 includes a variable delaycircuit 59 shown in FIG. 15. Accordingly, a period during which thepulse width of a second control signal GATE is extended can be variable.In the other respects, the fifth embodiment may be similar to the thirdembodiment.

If the on-duty ratio of a first control signal DDRV is larger than orequal to a predetermined value, a switching control circuit 50 amaintains the second control signal GATE in a deactivated state during aperiod during which the first control signal DDRV is deactivated, and ifthe on-duty ratio of the first control signal DDRV is smaller than thepredetermined value, the switching control circuit 50 a maintains thesecond control signal GATE in an activated state during a predeterminedperiod after the first control signal DDRV transits from an activatedstate to a deactivated state.

In that case, a configuration may be adopted in which, if the on-dutyratio of the first control signal DDRV is a first value, the switchingcontrol circuit 50 a sets the predetermined period to a first period,and if the on-duty ratio of the first control signal DDRV is a secondvalue that is smaller than the first value, the switching controlcircuit 50 a sets the predetermined period to a second period that islonger than the first period. That makes it possible to further increaseenergy that is accumulated in an inductor L1 if a period during which acurrent is caused to flaw to a light-emitting element 110 in digitallight control is shorter.

For example, five types of light control modes are set according to theon-duty ratio of the first control signal DDRV, and information forspecifying the current light control mode is supplied to a conditionsetting circuit 58. In a light control mode in which the on-duty ratioof the first control signal DDRV is larger than or equal to 5%, thecondition setting circuit 58 sets the predetermined period to 0, and ina light control mode in which the on-duty ratio of the first controlsignal DDRV is 4%, the condition setting circuit 58 sets thepredetermined period to TA1 (TA1>0).

In addition, in a light control mode in which the on-duty ratio of thefirst control signal DDRV is 3%, the condition setting circuit 58 setsthe predetermined period to TA2 (TA2>TA1), in a light control mode inwhich the on-duty ratio of the first control signal DDRV is 2%, thecondition setting circuit 58 sets the predetermined period to TA3(TA3>TA2), and in a light control mode in which the on-duty ratio of thefirst control signal DDRV is 1%, the condition setting circuit 58 setsthe predetermined period to TA4 (TA4>TA3).

Furthermore, the light emission control circuit 100 shown in FIG. 8 mayinclude circuits from a comparator 79 to a pulse width extension circuit82 shown in FIG. 14. In that case, the switching control circuit 50 amay adjust the predetermined period in accordance with a selectionsignal SEL that is supplied from the pulse width extension circuit 82,according to a current that flows to the light-emitting element 110.Accordingly, if a current that flows to the light-emitting element 110is smaller, it is possible to further increase energy that isaccumulated in the inductor L1.

For example, if a current that flows to the light-emitting element 110when the first control signal DDRV is activated is smaller than apredetermined value, the up-down counter 81 increments the count valueevery time a digital light control signal DCS is activated anddeactivated, and thus the difference between the count value and theinitial value increases gradually. The pulse width extension circuit 82successively generates selection signals SEL for selecting an outputsignal of a delay circuit having a delay time TD that is based on thedifference between the count value and the initial value, and suppliesthe selection signals SEL to the switching control circuit 50 a.

In the variable delay circuit 59 (FIG. 15) provided in the switchingcontrol circuit 50 a, a selection circuit 59 a successively selectsoutput signals of the delay circuit having the delay time TD thatgradually increases, in accordance with the selection signals SEL.Accordingly, the extension period of the pulse width of the secondcontrol signal GATE increases gradually.

Alternatively, if the on-duty ratio of the first control signal DDRV issmaller than the predetermined value, if a current that flows to thelight-emitting element 110 when the first control signal DDRV isactivated is smaller than the predetermined value, the switching controlcircuit 50 a may extend, by a first period, a period during which thesecond control signal GATE is maintained in an activated state after thefirst control signal DDRV transits from an activated state to adeactivated state, and if the current that flows to the light-emittingelement 110 when the first control signal DDRV is activated is largerthan the predetermined value, the switching control circuit 50 a mayshorten, by a second period, the period during which the second controlsignal GATE is maintained in an activated state after the first controlsignal DDRV transits from an activated state to a deactivated state.

In that case, it is desirable that the second period is longer than thefirst period. For example, in a case where the on-duty ratio of thefirst control signal DDRV changes from the first value (e.g., 1%) to thesecond value (e.g., 2%) that is larger than the first value, if thesecond control signal GATE is generated in accordance with an extensionperiod that was set when the on-duty ratio was the first value, acurrent that flows to the light-emitting element 110 becomes excessive.In view of this, when an extension period is set next time, an excessivecurrent can be resolved at an early stage by shortening the extensionperiod by the second period that is longer than the first period. Forexample, the second period may be twice the first period.

Sixth Embodiment

FIG. 17 is a circuit diagram showing a configuration example of a lightsource apparatus that has a light emission control circuit according toa sixth embodiment of the invention. In the sixth embodiment, in placeof the switching control circuit 50 shown in FIG. 1 or 4, a switchingcontrol circuit 50 c is used. In addition, a detection circuit 90 thatcompares the potential difference between the two ends of alight-emitting element 110 with a reference voltage VREF is added. Inthe other respects, the sixth embodiment may be similar to the first orsecond embodiment.

As shown in FIG. 17, the detection circuit 90 includes resistors R7 toR10, an operational amplifier 91, and a comparator 92, and may furtherincludes DAC 93 and a switch circuit 94. The resistors R7 and R8constitute a first voltage dividing circuit that divides a power supplypotential VDD. The resistors R9 and R10 constitute a second voltagedividing circuit that divides a detection potential VLD at theconnection point between a capacitor C4 and an inductor L1. The voltagedividing ratio of the first voltage dividing circuit and the voltagedividing ratio of the second voltage dividing circuit may be equal.

Accordingly, the first and second voltage dividing circuits divide thepotential difference between the two ends of the capacitor C4 by apredetermined voltage dividing ratio, and for example, the operationalamplifier 91 that operates when power supply potentials of 5 V and 0 Vare supplied amplifies the divided potential difference at apredetermined amplification factor. A transistor QP1 cyclically entersan on-state in accordance with a first control signal DDRV, and thus thepotential difference between the two ends of the capacitor C4 is thensubstantially equal to the potential difference between the two ends ofthe light-emitting element 110.

The comparator 92 compares an output voltage of the operationalamplifier 91 with the reference voltage VREF, and thereby generates anoutput signal VCOMP that is based on the comparison result. In thismanner, if the potential difference between the two ends of thelight-emitting element 110 is smaller than a predetermined value, thedetection circuit 90 deactivates the output signal VCOMP to a low level,and if the potential difference between the two ends of thelight-emitting element 110 is larger than the predetermined value, thedetection circuit 90 activates the output signal VCOMP to a high level.

An external microcomputer or the like may supply, to the detectioncircuit 90, the reference voltage VREF that is used for detectingwhether the potential difference between the two ends of thelight-emitting element 110 is smaller or larger than the predeterminedvalue. Alternatively, the detection circuit 90 may receive information(data) DREF regarding the reference voltage VREF from an externalmicrocomputer or the like. DAC 93 converts the data DREF that issupplied from outside, into the reference voltage VREF.

In that case, even if the voltage-current property of the light-emittingelement 110 changes due to a temperature, a change due to a temperaturecan be compensated by setting the reference voltage VREF that is basedon a temperature, from a microcomputer or the like that has temperatureinformation of the light source apparatus. Furthermore, a configurationmay be adopted in which the switch circuit 94 is provided, and one ofthe reference voltage VREF that is supplied from outside and thereference voltage VREF that is supplied from DAC 93 can be selected. Theoutput signal VCOMP of the detection circuit 90 is supplied to theswitching control circuit 50 c.

The switching control circuit 50 c activates or deactivates a secondcontrol signal GATE based on a clock signal CLK, a reset signal RST, theoutput signal VCOMP of the detection circuit 90, and a digital lightcontrol signal DCS that is supplied from a level shifter 21, in order tobring a transistor QN1 into an on-state or an off-state.

FIG. 18 is a circuit diagram showing a configuration example of theswitching control circuit shown in FIG. 17. In this example, theswitching control circuit 50 c includes an RS flip flop 51, an ANDcircuit 52, and an inverter 53.

The RS flip flop 51 activates an output signal to a high level insynchronization with the clock signal CLK, and deactivates the outputsignal in synchronization with the reset signal RST that is generatedbased on a current that flows through the transistor QN1 and a currentthat flows through the light-emitting element 110. The AND circuit 52corresponds to a mask circuit that masks an output signal of the RS flipflop 51 in accordance with the output signal VCOMP of the detectioncircuit 90.

In a case of stopping the RS flip flop 51 or the circuits of thefeedback group in order to mask an output signal of the RS flip flop 51,restoration of the second control signal GATE takes time, but in a caseof masking an output signal of the RS flip flop 51, a time required forrestoring the second control signal GATE can be shortened.

The inverter 53 inverts the output signal VCOMP of the detection circuit90, and supplies the inverted output signal VCOMP to the AND circuit 52.In a case where the output signal VCOMP of the detection circuit 90 isdeactivated to a low level and an output signal of the inverter 53 is ata high level, the AND circuit 52 outputs an output signal of the RS flipflop 51 as the second control signal GATE, and in a case where theoutput signal VCOMP of the detection circuit 90 is activated to a highlevel and an output signal of the inverter 53 is at a low level, the ANDcircuit 52 maintains the second control signal GATE in an activatedstate.

Exemplary Operation

An exemplary operation of the light emission control circuit accordingto the sixth embodiment of the invention will be described withreference to FIGS. 17 to 19. FIG. 19 is a waveform diagram forillustrating an exemplary operation of the light emission controlcircuit shown in FIG. 17. FIG. 19 shows a case where the on-duty ratioof a digital light control signal (the on-duty ratio of the firstcontrol signal DDRV) is smaller than a predetermined value.

When the digital light control signal DCS is activated to a high level,the first control signal DDRV is activated to a low level, thetransistor QP1 enters an on-state, and a current ILD flows to thelight-emitting element 110. Accordingly, when the detection potentialVLD rises above a threshold and the potential difference between the twoends of the light-emitting element 110 becomes smaller than apredetermined value, the output signal VCOMP of the detection circuit 90is deactivated to a low level.

When the output signal VCOMP of the detection circuit 90 is deactivatedto a low level, the AND circuit 52 outputs an output signal of the RSflip flop 51 as the second control signal GATE. Accordingly, if thepotential difference between the two ends of the light-emitting element110 is smaller than the predetermined value, the switching controlcircuit 50 c activates the second control signal GATE during at least aportion of the period in order to bring the transistor QN1 into anon-state.

When the second control signal GATE is activated to a high level, thetransistor QN1 enters an on-state, and a current IL flows to theinductor L1. The current IL that flows to the inductor L1 graduallyincreases over time. During the period shown in FIG. 19, the current ILthat flows to the inductor L1 is small, and thus the reset signal RSTthat is output from the comparator 75 is at a low level.

After that, when the digital light control signal DCS is deactivated toa low level, the first control signal DDRV is deactivated to a highlevel, the transistor QP1 enters an off-state, and the current ILD tothe light-emitting element 110 stops. Accordingly, a current is notsupplied from the light-emitting element 110 to the inductor L1 anylonger, and thus the detection potential VLD falls gradually. When thedetection potential VLD falls below a threshold and the potentialdifference between the two ends of the light-emitting element 110exceeds the predetermined value, the output signal VCOMP of thedetection circuit 90 is activated to a high level.

When the output signal VCOMP of the detection circuit 90 is activated toa high level, the AND circuit 52 deactivates an output signal to a lowlevel. Accordingly, if the potential difference between the two ends ofthe light-emitting element 110 is larger than the predetermined value,the switching control circuit 50 c maintains the second control signalGATE in a deactivated state in order to bring the transistor QN1 into anoff-state.

When the second control signal GATE is deactivated to a low level, thetransistor QN1 enters an off-state, the current IL that flows to theinductor L1 decreases, and fall of the detection potential VLD stops. Inthis manner, the switching control circuit 50 c adjusts activation anddeactivation of the second control signal GATE such that the potentialdifference between the two ends of the light-emitting element 110approaches the predetermined value.

Although not shown in FIG. 19, if the on-duty ratio of the digital lightcontrol signal DCS is larger than or equal to a predetermined value,there are cases where the reset signal RST is activated before theoutput signal VCOMP of the detection circuit 90 is activated. In thatcase, the switching control circuit 50 c deactivates the second controlsignal GATE in synchronization with activation of the reset signal RST.Furthermore, there are cases where the switching control circuit 50 crepeats activation and deactivation of the second control signal GATE insynchronization with the clock signal CLK and the reset signal RST.

According to the sixth embodiment, if the potential difference betweenthe two ends of the light-emitting element 110 is larger than thepredetermined value, the transistor QN1 is maintained in an off-state bymaintaining the second control signal GATE for analog light control in adeactivated state. Accordingly, in a case of performing both analoglight control and digital light control, even if the first controlsignal DDRV for digital light control is deactivated and the transistorQP1 enters an off-state, it is possible to suppress discharge of energyaccumulated in the inductor L1 without being used for light emission,and reduce power loss.

In addition, if the potential difference between the two ends of thelight-emitting element 110 is smaller than the predetermined value, thetransistor QN1 enters an on-state by activating the second controlsignal GATE for analog light control during at least a portion of theperiod. Accordingly, even if a period during which a current is causedto flow to the light-emitting element 110 in digital light control isshort, it is possible to accumulate energy in the inductor L1, andprevent reduction of a current that flows to the light-emitting element110 below a current instructed in analog light control.

Seventh Embodiment

FIG. 20 is a circuit diagram showing a configuration example of aswitching control circuit of a seventh embodiment of the invention. Inthe seventh embodiment, a switching control circuit 50 d shown in FIG.20 is used in place of the switching control circuit 50 c in the sixthembodiment shown in FIG. 17. In the other respects, the seventhembodiment may be similar to the sixth embodiment.

A light emission control circuit 100 receives information regarding theon-duty ratio of a digital light control signal DCS, that is informationregarding the on-duty ratio of a first control signal DDRV, from anexternal microcomputer or the like. Accordingly, the switching controlcircuit 50 d can set a condition for activation or deactivation of asecond control signal GATE based on the information regarding theon-duty ratio of the first control signal DDRV.

In the example shown in FIG. 20, the switching control circuit 50 dincludes an RS flip flop 51, an AND circuit 52, an inverter 53, and anOR circuit 57. In addition, a mode signal MOD that is set to a highlevel if the on-duty ratio of the first control signal DDRV is largerthan or equal to a predetermined value, and is set to a low level if theon-duty ratio of the first control signal DDRV is smaller than thepredetermined value is supplied to the switching control circuit 50 d.

For example, two types of light control modes are set according to theon-duty ratio of the first control signal DDRV. In a first light controlmode, the on-duty ratio of the first control signal DDRV is larger thanor equal to 5% and smaller than or equal to 100%, in a second lightcontrol mode, the on-duty ratio of the first control signal DDRV islarger than 0% and smaller than 5%. In that case, the mode signal MOD isat a high level in the first light control mode, and is at a low levelin the second light control mode.

When the reset signal RST is at a low level, the RS flip flop 51 is setin synchronization with rise of the clock signal CLK, and activates anoutput signal to a high level, and when the clock signal CLK is at a lowlevel, the RS flip flop 51 is reset in synchronization with rise of thereset signal RST, and deactivates an output signal to a low level.

The inverter 53 inverts the mode signal MOD so as to generate an outputsignal. The OR circuit 57 generates an output signal by obtaining thelogical sum of the digital light control signal DCS and the outputsignal of the inverter 53. The AND circuit 52 generates an output signalby obtaining the logical product of an output signal of the RS flip flop51 and an output signal of the OR circuit 57.

If the on-duty ratio of the first control signal DDRV is larger than orequal to the predetermined value, the mode signal MOD is set to a highlevel, an output signal of the inverter 53 is set to a low level, andthe OR circuit 57 supplies the digital light control signal DCS to oneinput terminal of the AND circuit 52. When the digital light controlsignal DCS is activated to a high level, the AND circuit 52 outputs anoutput signal of the RS flip flop 51 as the second control signal GATE,and when the digital light control signal DCS is deactivated to a lowlevel, deactivates the output signal to a low level.

Accordingly, if the on-duty ratio of the first control signal DDRV islarger than or equal to the predetermined value, the switching controlcircuit 50 d activates or deactivates the second control signal GATE inorder to bring a transistor QN1 into an on-state or an off-state duringa period during which the first control signal DDRV is activated, andmaintains the second control signal GATE in a deactivated state during aperiod during which the first control signal DDRV is deactivated.

On the other hand, if the on-duty ratio of the first control signal DDRVis smaller than the predetermined value, the mode signal MOD is set to alow level, an output signal of the inverter 53 is set to a high level,and the OR circuit 57 supplies the high-level signal to one inputterminal of the AND circuit 52. The AND circuit 52 outputs an outputsignal of the RS flip flop 51 as the second control signal GATE,

Accordingly, if the on-duty ratio of the first control signal DDRV issmaller than the predetermined value, the switching control circuit 50 dactivates or deactivates the second control signal GATE asynchronouslywith the first control signal DDRV. The transistor QN1 is in an on-statewhen the second control signal GATE is activated, and is in an off-statewhen the second control signal GATE is deactivated.

According to the seventh embodiment, if the on-duty ratio of the firstcontrol signal DDRV for digital light control is larger than or equal tothe predetermined value, the transistor QN1 is maintained in anoff-state by maintaining the second control signal GATE for analog lightcontrol in a deactivated state during a period during which the firstcontrol signal DDRV is deactivated. Accordingly, in a case of performingboth analog light control and digital light control, it is possible tosuppress discharge of energy accumulated in the inductor L1 withoutbeing used for light emission, and reduce power loss.

In addition, if the on-duty ratio of the first control signal DDRV fordigital light control is smaller than the predetermined value, thetransistor QN1 enters an on-state or an off-state asynchronously withthe first control signal DDRV by activating or deactivating the secondcontrol signal GATE for analog light control asynchronously with thefirst control signal DDRV. Accordingly, even in a case where a periodduring which a current is caused to flow to the light-emitting element110 in digital light control is short, it is possible to accumulateenergy in the inductor L1, and prevent reduction of a current that flowsto the light-emitting element 110 below a current instructed in analoglight control.

Eighth Embodiment

In the light source apparatus that has been described above, anN-channel MOS transistor can also be used in place of the P-channel MOStransistor QP1 as the first switching element. As an example, a casewill be described below in which an N-channel MOS transistor is used asthe first switching element in the light source apparatus shown in FIG.1.

FIG. 21 is a circuit diagram showing a configuration example of a lightsource apparatus that has a light emission control circuit according tothe eighth embodiment of the invention. As shown in FIG. 21, in thislight source apparatus, an N-channel MOS transistor QN5 is used as thefirst switching element, and diodes D2 and D3, a Zener diode D4, aresistor R11, capacitors C6 and C7 are added.

The transistor QN5 has a drain connected to a light-emitting element110, a source connected to one end of an inductor L1, and a gate towhich a first control signal DDRV is applied. A driving circuit 30 aactivates the first control signal DDRV to a high level in order tobring the transistor QN5 into an on-state, in accordance with a digitallight control signal DCS, and deactivates the first control signal DDRVto a low level in order to bring the transistor QN5 into an off-state.

The first control signal DDRV and a second control signal GATE transitbetween a low level (e.g., 0 V) and a high level (e.g., 7.5 V). When thefirst control signal DDRV is activated to a high level, a current flowsfrom the driving circuit 30 a to the gate of the transistor QN5 via thecapacitor C6, the voltage between the gate and the source of thetransistor QN5 rises, and the transistor QN5 enters an on-state. TheZener diode D4 clamps such that the voltage between the gate and thesource of the transistor QN5 does not exceed a predetermined voltage(e.g., 7.5 V).

A third control signal GATE′ transits between a low level and a highlevel during a period during which the first control signal DDRV ismaintained in an activated state. Accordingly, the capacitor C7 and thediodes D2 and D3 perform a rectifying operation, and thus the voltagebetween the gate and the source of the transistor QN5 is maintained at athreshold voltage or more. In the example shown in FIG. 21, the secondcontrol signal GATE is maintained in a deactivated state during adeactivation period of the first control signal DDRV, and thus thesecond control signal GATE can also be used as the third control signalGATE′.

On the other hand, in the sixth embodiment shown in FIG. 17, also duringa deactivation period of the first control signal DDRV, the secondcontrol signal GATE can be activated and deactivated, and thus the thirdcontrol signal GATE′ that is different from the second control signalGATE is used. For example, by providing, in the switching controlcircuit 50, an AND circuit for obtaining the logical product of thedigital light control signal DCS or the first control signal DDRV andthe second control signal GATE, the third control signal GATE′ isgenerated.

When the first control signal DDRV is deactivated to a low level, acurrent flows from the source of the transistor QN5 to the drivingcircuit 30 a via the diodes D2 and D3 and the capacitor C6, the voltagebetween the gate and the source of the transistor QN5 falls, and thetransistor QN5 enters an off-state. In a case where the light emissionapparatus stops light emission for a long time at the time of stand-byor the like, the resistor R11 drops the voltage between the gate and thesource of the transistor QN5, and maintains the transistor QN5 in anoff-state.

According to the above embodiment, it is possible to provide a lightsource apparatus in which power loss is small and that can accuratelycontrol brightness by the light emission control circuit 100 suppressingdischarge of energy accumulated in the inductor L1 without being usedfor light emission, and preventing a reduction in a current that flowsto the light-emitting element 110 even in a case where a period duringwhich a current is caused to flow to the light-emitting element 110 indigital light control is short.

In addition, the light emission control circuit 100 may receive, from anexternal microcomputer or the like, the first control signal DDRV andthe second control signal GATE that has been adjusted according to theon-duty ratio of the first control signal DDRV, and perform lightemission control.

Projection-type Video Display Device

Next, a projection-type video display device (video projector) accordingto one embodiment of the invention will be described.

FIG. 22 is a block diagram showing a configuration example of theprojection-type video display device according to one embodiment of theinvention. A projection-type video display device 200 is a displaydevice to which a power supply voltage is supplied from outside, towhich image data is supplied from an image data supply apparatus such asa personal computer or a video player, and that projects an image on ascreen (a projection surface) 300 based on the image data.

As shown in FIG. 22, the projection-type video display device 200includes a power supply circuit 210, an image data processor 220, acontroller 230, a light source apparatus 240, a panel 250, and theprojection optical system 260. The light source apparatus 240 includes alight emission control circuit 100 and a light-emitting element 110.

The power supply circuit 210 generates a logic power supply voltagebased on a power supply voltage of AC 100V supplied from outside, forexample, and supplies the logic power supply voltage to the image dataprocessor 220, the controller 230, and the like, and generates a powersupply voltage of about DC50V, and supplies the power supply voltage tothe light emission control circuit 100 of the light source apparatus240, and the like. The light emission control circuit 100 generates aninternal power supply voltage of about DC30 to 40V based on the powersupply voltage of about DC50V, for example.

The image data processor 220 and the controller 230 are constituted byone or more microcomputers and the like, for example. The image dataprocessor 220 processes image data supplied from outside, generatesimage signals for display and a synchronization signal, supplies theimage signals and the synchronization signal to the panel 250, andthereby drives the panel 250 so as to perform image formation.

The controller 230 controls the constituent elements of theprojection-type video display device 200 in accordance with an operationperformed by an operator using a remote controller or an operation panel(not illustrated). In a case where the operator instructs light control,the controller 230 generates a digital light control signal DCS and ananalog light control signal ACS for carrying out light controlinstructed by the operator, and supplies those signals to the lightemission control circuit 100 of the light source apparatus 240.

The light source apparatus 240 emits light with brightness that is basedon the digital light control signal DCS and the analog light controlsignal ACS supplied from the controller 230, and irradiates the panel250 with the light. For example, in a case where the light-emittingelement 110 includes a plurality of laser diodes that generate bluelight, the light source apparatus 240 may further include a phosphorthat receives the blue light generated by a portion of the laser diodesand generates yellow light, and a spectroscope that separates red lightand green light from yellow light in accordance with the wavelength. Inthat case, the light source apparatus 240 can generate light of threecolors, namely, R (red), G (green), and B (blue).

The panel 250 modulates light emitted from the light source apparatus240, in accordance with image signals and a synchronization signalsupplied from the image data processor 220. For example, the panel 250may include three liquid crystal panels that correspond to the three RGBcolors. Each of the liquid crystal panels forms an image by changing thetransmissivity of light in a plurality of pixels arranged in matrix.Modulated light modulated by the panel 250 is guided to the projectionoptical system 260.

The projection optical system 260 includes at least one lens. Forexample, a projection lens that is a lens group for forming an image byprojecting, on the screen 300, modulated light modulated by the panel250, and various mechanisms that change the state of the diaphragm ofthe projection lens, the state of the zooming, the shift position, orthe like are provided in the projection optical system 260. Thosemechanisms are controlled by the controller 230. By the projectionoptical system 260 projecting modulated light on the screen 300, animage is displayed on the screen 300. According to this embodiment, itis possible to accurately control the luminance of a projected imagewhile reducing the power consumption of the projection-type videodisplay device, using the light source apparatus 240 in which power lossis small and that can accurately control brightness.

The invention is not limited to the embodiments given above, and aperson having ordinary skill in the art can make many modificationswithin the technical concept of the invention. For example, a pluralityof embodiments selected from the embodiments given above can be combinedand implemented

What is claimed is:
 1. A light emission control circuit that controls afirst switching element for controlling a current that flows to alight-emitting element connected between a first node and one end of aninductor and a second switching element for controlling a current thatflows from the other end of the inductor to a second node, the lightemission control circuit comprising: a driving circuit that generates afirst control signal for controlling the first switching element; and aswitching control circuit that generates a second control signal forcontrolling the second switching element, and deactivates the secondcontrol signal in order to bring the second switching element into anoff-state during at least a portion of a period during which the firstcontrol signal is deactivated by the driving circuit in order to bringthe first switching element into an off-state,
 2. The light emissioncontrol circuit according to claim 1, wherein the switching controlcircuit maintains the second control signal in a deactivated stateduring a period during which the first control signal is deactivated ifan on-duty ratio of the first control signal is larger than or equal toa predetermined value, and maintains the second control signal in anactivated state during a portion of the period during which the firstcontrol signal is deactivated if the on-duty ratio of the first controlsignal is smaller than the predetermined value.
 3. The light emissioncontrol circuit according to claim 2, wherein if the on-duty ratio ofthe first control signal is smaller than the predetermined value, theswitching control circuit maintains the second control signal in anactivated state during a predetermined period after the first controlsignal transits from an activated state to a deactivated state.
 4. Thelight emission control circuit according to claim 3, wherein if theon-duty ratio of the first control signal is smaller than thepredetermined value, and the second control signal has never beendeactivated during a period during which the first control signal isactivated, the switching control circuit maintains the second controlsignal in an activated state during the predetermined period.
 5. Thelight emission control circuit according to claim 3, wherein if theon-duty ratio of the first control signal is a first value, theswitching control circuit sets the predetermined period to a firstperiod, and if the on-duty ratio of the first control signal is a secondvalue that is smaller than the first value, sets the predeterminedperiod to a second period that is longer than the first period.
 6. Thelight emission control circuit according to claim 3, wherein theswitching control circuit adjusts the predetermined period according toa current that flows to the light-emitting element. The light emissioncontrol circuit according to claim 2, wherein in a case where theon-duty ratio of the first control signal is smaller than thepredetermined value, the switching control circuit extends, by a firstperiod, a period during which the second control signal is maintained inan activated state after the first control signal transits from anactivated state to a deactivated state if a current that flows to thelight-emitting element when the first control signal is activated issmaller than the predetermined value, and shortens, by a second period,the period during which the second control signal is maintained in anactivated state after the first control signal transits from anactivated state to a deactivated state if a current that flows to thelight-emitting element when the first control signal is activated islarger than the predetermined value.
 8. The light emission controlcircuit according to claim 7, wherein the second period is longer thanthe first period.
 9. The light emission control circuit according toclaim 2, wherein information regarding the on-duty ratio of the firstcontrol signal is received from outside.
 10. A light emission controlcircuit that controls a first switching element for controlling acurrent that flows to a light-emitting element connected between a firstnode and one end of an inductor and a second switching element forcontrolling a current that flows from the other end of the inductor to asecond node, the light emission control circuit comprising: a drivingcircuit that activates or deactivates a first control signal in order tobring the first switching element into an on-state or an off-state; anda switching control circuit that activates or deactivates a secondcontrol signal in order to bring the second switching element into anon-state or an off-state during a period during which the first controlsignal is activated, shortens a period during which activation of thesecond control signal is inhibited in a period during which the firstcontrol signal is deactivated, if a current that flows to thelight-emitting element when the first control signal is activated issmaller than a predetermined value, and extends the period during whichactivation of the second control signal is inhibited in the periodduring which the first control signal is deactivated, if the currentthat flows to the light-emitting element when the first control signalis activated is larger than the predetermined value.
 11. The lightemission control circuit according to claim 6, further comprising: asample hold circuit that samples and holds a voltage that is inproportion to a current that flows to the light-emitting element whenthe first control signal is activated.
 12. A light source apparatuscomprising: the light emission control circuit according to claim 1; thelight-emitting element, the inductor, the first and second switchingelements; a capacitor connected between one end of the inductor and afirst node; and a diode connected between the other end of the inductorand the first node, wherein when the first and second switching elementsare in an on-state, a current flows to the light-emitting element andthe inductor, and energy is accumulated in the inductor, when the firstswitching element is in an on-state and the second switching element isin an off-state, a current flows to the light-emitting element and thediode due to energy accumulated in the inductor, and when the firstswitching element is in an off-state and the second switching element isin an on-state, a current flows to the capacitor and the inductor, andenergy is accumulated in the inductor.
 13. A projection-type videodisplay device comprising: the light source apparatus according to claim12.